Field of the Invention
The invention relates to a memory device and particularly relates to a dynamic random access memory with buried word lines.
Description of Related Art
A dynamic random access memory (DRAM) is a volatile memory formed by a plurality of memory cells. Each of the memory cells is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are electrically connected with one another through word lines and bit lines.
In order to improve the integration of DRAM to increase the operating speed of the device and to meet the consumers' demand for miniaturization of electronic devices, buried word line DRAM has been developed in recent years for such purposes.
A dominant layout of the currently used DRAM is that two memory cells share one bit line contact and the two memory cells are controlled by two word lines respectively. However, when the word line of one of the memory cells is turned on/off for controlling one of the memory cells, the other memory cell that shares the bit line contact with the aforementioned memory cell may be interfered with easily. In such circumstances, the interference will become more serious if the memory cell feature size is miniaturized (that is, the distance between the memory cells is shortened).
In addition, since the pitch between the word lines is only one feature size, when the word line is drawn to the edge of the memory cell array for fabricating a word line pick up contact, short circuit may easily occur between the word line pick up contact and the word line during the fabrication. One conventional method is to separate two adjacent word lines by a distance at the end to form an approximately Y-shaped structure, so as to increase the process window for fabricating the contact. However, such a method will occupy additional area on the edge of the memory cell array and cause the chip size to increase. Furthermore, the design of pick up contacts from both ends of the word line to the edge of the memory cell array will not be applicable. Thus, loss due to broken word lines cannot be reduced.
Moreover, capacitor contacts are respectively disposed on two ends of the memory cell layout and the bridge window for the capacitor contacts is determined by the pitch between two adjacent capacitor contacts. According to the current layout, the pitch between two adjacent capacitor contacts is only one feature size (1F). Due to the limitation of the layout design, as the fabrication is miniaturized, the bridge window for the capacitor contacts will become even smaller.